As global demand for ultra-fast wireless communication continues to rise, engineers are being pushed toward an uncomfortable reality. Existing wireless technologies are approaching their physical and architectural limits. Streaming platforms, artificial intelligence systems, cloud computing infrastructure, autonomous machines, and next-generation data centres all require enormous amounts of data to move faster and more efficiently than current systems can comfortably handle.
To meet those demands, researchers are increasingly turning their attention toward frequencies above 100 GHz, often referred to as the sub terahertz range. These frequencies offer massive unused bandwidth capable of supporting future 6G communication networks and ultra high speed wireless links. Yet operating in this region introduces severe technical challenges that conventional receiver architectures struggle to overcome.
A team of researchers from the University of California, Irvine has now demonstrated a potential solution. In a recently published study titled “An Antenna to Bits F Band 120 Gbps CMOS RF 64QAM Receiver” in the IEEE Journal of Solid State Circuits, first author Youssef O. Hassan and colleagues presented a CMOS-based wireless receiver capable of achieving real-time 120 Gbps communication at frequencies between 100 and 140 GHz. The work represents an important advance in low-power sub-terahertz receiver design and could help shape future high-speed wireless communication systems.
Why wireless systems are reaching a breaking point
Modern wireless communication systems rely heavily on digital signal processing. Signals received by antennas are typically converted to digital form using extremely high-speed analog-to-digital converters before undergoing complex processing steps. While this approach has proven highly effective for current mobile and Wi Fi technologies, it becomes increasingly inefficient at extremely high frequencies and data rates.
At speeds above 100 Gbps, analogue to digital converters must operate at hundreds of gigasamples per second. Such systems consume substantial power and require highly sophisticated clocking and calibration circuitry. As frequencies climb closer to transistor operating limits, maintaining signal quality, timing precision and energy efficiency becomes exceptionally difficult.
The University of California, Irvine researchers identified this growing bottleneck as one of the central problems limiting future 6G development. Rather than relying on traditional digital heavy architectures, the team pursued a fundamentally different strategy that shifts much of the signal interpretation process into the analogue domain.
This alternative architecture dramatically reduces the need for power hungry digital conversion and signal processing stages. According to the researchers, the approach enables high order modulation schemes such as 64QAM while significantly lowering system complexity and power consumption.
A different approach to decoding wireless signals
One of the most distinctive aspects of the receiver is its “antenna to bits” architecture. Instead of passing signals through large digital processing chains, the system performs direct analogue domain demodulation, extracting information rapidly and efficiently from incoming wireless signals.
The receiver uses a hierarchical demodulation method that progressively breaks down complex 64QAM constellations into simpler signal groups. In practical terms, this means the system can determine transmitted data bits in several smaller and faster stages rather than processing the entire signal at once.
This sequential analogue processing method allows the receiver to recover data with remarkably low latency. The architecture avoids many of the timing and power limitations associated with synchronous digital processing systems that dominate modern communication hardware.
Operating at the frontier of wireless frequencies
The receiver operates in the F band between 100 and 140 GHz, a region increasingly viewed as a promising candidate for future 6G wireless communication systems. These frequencies offer enormous contiguous bandwidth that could support applications requiring ultra-high data throughput.
Potential applications include wireless data centre interconnects, high-speed backhaul infrastructure, secure short-range communication systems and advanced edge computing networks. Researchers have also suggested that sub-terahertz wireless systems could eventually complement or partially replace short-range fiber optic connections in certain specialized environments.
However, designing circuits at these frequencies is notoriously difficult. As transistors approach their maximum operating frequencies, gain drops sharply and signal losses increase significantly. Maintaining acceptable noise performance, linearity and reliability becomes a major engineering challenge.
To address these problems, the team developed a highly integrated receiver front end that combines a wideband low noise amplifier, active IQ mixer and programmable equalisation stages. The system also includes an integrated on chip helical antenna supported by a silicon lens structure designed to reduce substrate losses and improve radiation efficiency.
According to the study, the antenna achieved a simulated gain of approximately 12 dBi at 120 GHz while maintaining wide bandwidth performance. The complete receiver achieved a peak conversion gain of 32 dB with a minimum noise figure of 9.5 dB across a 40 GHz bandwidth.
Building high-speed wireless hardware in CMOS
One of the most significant aspects of the research is the use of 22 nm FDSOI CMOS technology. CMOS manufacturing remains one of the most scalable and commercially important semiconductor fabrication platforms worldwide. Demonstrating sub-terahertz communication hardware in CMOS suggests that future ultra-high-speed wireless systems may eventually become more practical and cost-effective to manufacture.
Historically, many high-frequency communication systems have relied on specialised, expensive semiconductor technologies such as SiGe BiCMOS. While these technologies offer excellent high-frequency performance, they often come with greater manufacturing complexity and higher costs.
The University of California, Irvine team instead demonstrated that advanced nanoscale CMOS can successfully support demanding sub terahertz receiver architectures. The prototype occupied an area of 2.5 × 3 mm² and consumed approximately 230 mW of power.
The researchers also designed a sophisticated local oscillator generation network capable of producing stable 120 GHz signals from a lower frequency 30 GHz reference input. This subsystem was essential for supporting accurate IQ mixing and high-order modulation schemes such as 64QAM.
Demonstrating 120 Gbps wireless communication
To validate the receiver experimentally, the researchers performed a series of wireless link measurements over a 15 cm transmission distance. The system successfully demonstrated real-time demodulation of QPSK, 16QAM, and 64QAM signals at data rates reaching 120 Gbps.
The experiments showed that the receiver could maintain acceptable error vector magnitude performance even under demanding operating conditions. The researchers reported measured EVM values of approximately minus 12 dB for QPSK, minus 17.5 dB for 16QAM and minus 17.2 dB for 64QAM.
The receiver also achieved a bit-error rate of 10⁻² for 64QAM operation at a received power level of -32 dBm. While the system remains an experimental research prototype rather than a commercial communication product, these measurements demonstrate that high-speed analog domain demodulation at sub-terahertz frequencies is technically feasible.
Importantly, the receiver maintained robust signal integrity during testing. Measured eye diagrams remained wide open across multiple data rates, indicating low inter-symbol interference and stable timing performance.
The broader race toward 6G
The work arrives amid growing global investment in 6G research and sub terahertz communication technologies. Governments, semiconductor companies and academic laboratories worldwide are actively exploring architectures capable of supporting future wireless networks that may eventually exceed terabit per second data rates.
Although commercial deployment of sub-terahertz communication systems remains years away, research such as this provides critical building blocks for future development. High-speed, low-power receiver architectures will likely play an essential role in enabling practical next-generation wireless systems.
The analogue domain processing strategy demonstrated by Hassan and colleagues may also influence broader communication system design philosophies. As power efficiency becomes increasingly important across the semiconductor industry, reducing dependence on extremely high speed digital conversion could become an attractive approach in multiple application areas.
The researchers themselves noted that the architecture avoids many of the complexities associated with heavily interleaved analog-to-digital converters and large digital signal processing pipelines. This simplification could eventually help reduce system cost, chip area and power consumption in future wireless transceivers.
Reference
Hassan, Y. O., Oveisi, M., Wang, Z., & Heydari, P. (2026). An antenna to bits F band 120 Gbps CMOS RF 64QAM receiver. IEEE Journal of Solid State Circuits. https://doi.org/10.1109/JSSC.2025.3648748
